How to exploit 7th series Xilinx FPGA ODDR to emulate the full behaviour of the former ODDR2? A customised CDR loop which I designed requires the circuit in figure to be implemented inside the FPGA logic. It actually asserts the out signal synchronously to either the positive or the negative edge coming from the data path. The reset is properly handled by an external controller not shown. Originally it was fully implemented in the fabric logic in such a simple way:...